Can Wang, Guang Zhu, Zhao Zhang, C. Patrick Yue. A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. In 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019. pages 274, IEEE, 2019. [doi]
@inproceedings{WangZZY19-0,
title = {A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects},
author = {Can Wang and Guang Zhu and Zhao Zhang and C. Patrick Yue},
year = {2019},
doi = {10.23919/VLSIC.2019.8778159},
url = {https://doi.org/10.23919/VLSIC.2019.8778159},
researchr = {https://researchr.org/publication/WangZZY19-0},
cites = {0},
citedby = {0},
pages = {274},
booktitle = {2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {IEEE},
isbn = {978-4-86348-720-8},
}