Ted E. Williams, Mark A. Horowitz. A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. In 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991. pages 210-217, IEEE, 1991. [doi]
@inproceedings{WilliamsH91,
title = {A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages},
author = {Ted E. Williams and Mark A. Horowitz},
year = {1991},
doi = {10.1109/ARITH.1991.145561},
url = {http://dx.doi.org/10.1109/ARITH.1991.145561},
researchr = {https://researchr.org/publication/WilliamsH91},
cites = {0},
citedby = {0},
pages = {210-217},
booktitle = {10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991},
publisher = {IEEE},
isbn = {0-8186-9151-4},
}