A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

David Wilson, Aniruddha Shastri, Greg Stitt. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Int. J. Reconfig. Comp., 2017, 2017. [doi]

Authors

David Wilson

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Aniruddha Shastri

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Greg Stitt

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