David Wilson, Aniruddha Shastri, Greg Stitt. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. Int. J. Reconfig. Comp., 2017, 2017. [doi]
@article{WilsonSS17,
title = {A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance},
author = {David Wilson and Aniruddha Shastri and Greg Stitt},
year = {2017},
doi = {10.1155/2017/5419767},
url = {https://doi.org/10.1155/2017/5419767},
researchr = {https://researchr.org/publication/WilsonSS17},
cites = {0},
citedby = {0},
journal = {Int. J. Reconfig. Comp.},
volume = {2017},
}