Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang. Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains. In 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010. pages 358-366, IEEE Computer Society, 2010. [doi]
@inproceedings{WuWYFWJTZLCLJ10,
title = {Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains},
author = {Shianling Wu and Laung-Terng Wang and Lizhen Yu and Hiroshi Furukawa and Xiaoqing Wen and Wen-Ben Jone and Nur A. Touba and Feifei Zhao and Jinsong Liu and Hao-Jan Chao and Fangfang Li and Zhigang Jiang},
year = {2010},
doi = {10.1109/DFT.2010.50},
url = {http://doi.ieeecomputersociety.org/10.1109/DFT.2010.50},
researchr = {https://researchr.org/publication/WuWYFWJTZLCLJ10},
cites = {0},
citedby = {0},
pages = {358-366},
booktitle = {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010},
publisher = {IEEE Computer Society},
isbn = {978-1-4244-8447-8},
}