A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO - researchr publication authors

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Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang-Won Son, Thomas Byunghak Cho. A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. J. Solid-State Circuits, 56(12):3756-3767, 2021. [doi]

This author has not been identified. Look up 'Wanghua Wu' in GoogleThis author has not been identified. Look up 'Chih-Wei Yao' in GoogleThis author has not been identified. Look up 'Chengkai Guo' in GoogleThis author has not been identified. Look up 'Pei-Yuan Chiang' in GoogleThis author has not been identified. Look up 'Lei Chen' in GoogleThis author has not been identified. Look up 'Pak-Kim Lau' in GoogleThis author has not been identified. Look up 'Zhanjun Bai' in GoogleThis author has not been identified. Look up 'Sang-Won Son' in GoogleThis author has not been identified. Look up 'Thomas Byunghak Cho' in Google

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