Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang-Won Son, Thomas Byunghak Cho. A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. J. Solid-State Circuits, 56(12):3756-3767, 2021. [doi]
@article{WuYGCCLBSC21,
title = {A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO},
author = {Wanghua Wu and Chih-Wei Yao and Chengkai Guo and Pei-Yuan Chiang and Lei Chen and Pak-Kim Lau and Zhanjun Bai and Sang-Won Son and Thomas Byunghak Cho},
year = {2021},
doi = {10.1109/JSSC.2021.3111134},
url = {https://doi.org/10.1109/JSSC.2021.3111134},
researchr = {https://researchr.org/publication/WuYGCCLBSC21},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {56},
number = {12},
pages = {3756-3767},
}