A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

Lanhua Xia, Jianhui Wu, Zhikuang Cai. A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement. IEICE Electronic Express, 15(4):20171215, 2018. [doi]

Authors

Lanhua Xia

This author has not been identified. Look up 'Lanhua Xia' in Google

Jianhui Wu

This author has not been identified. Look up 'Jianhui Wu' in Google

Zhikuang Cai

This author has not been identified. Look up 'Zhikuang Cai' in Google