A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement

Lanhua Xia, Jianhui Wu, Zhikuang Cai. A self-refereed design-for-test structure of CP-PLL for on-chip jitter measurement. IEICE Electronic Express, 15(4):20171215, 2018. [doi]

Abstract

Abstract is missing.