The following publications are possibly variants of this publication:
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- Loop Scheduling with Complete Memory Latency Hiding on Multi-core ArchitectureChun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edwin Hsing-Mean Sha. icpads 2006: 375-382 [doi]
- Iterational retiming with partitioning: Loop scheduling with complete memory latency hidingChun Jason Xue, Jingtong Hu, Zili Shao, Edwin Hsing-Mean Sha. tecs, 9(3), 2010. [doi]
- Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memoryMeikang Qiu, Jiande Wu, Chun Jason Xue, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha. fpl 2008: 459-462 [doi]
- Loop Scheduling and Partitions for Hiding Memory LatenciesFei Chen, Edwin Hsing-Mean Sha. isss 1999: 64-70 [doi]
- Energy Minimization and Latency Hiding for Heterogeneous Parallel MemoryMeikang Qiu, Gang Wu, Jingtong Hu, Wei-Che Tseng, Edwin Hsing-Mean Sha. icpads 2009: 503-510 [doi]
- Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetchingZhong Wang, Timothy W. O'Neil, Edwin Hsing-Mean Sha. tsp, 49(11):2853-2864, 2001. [doi]
- Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applicationsZhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha. dac 2000: 540-545 [doi]