A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Shinji, Koji Nii. A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures. IEEE Trans. VLSI Syst., 26(11):2335-2344, 2018. [doi]

@article{YabuuchiTFTSN18,
  title = {A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures},
  author = {Makoto Yabuuchi and Yasumasa Tsukamoto and Hidehiro Fujiwara and Miki Tanaka and Shinji Shinji and Koji Nii},
  year = {2018},
  doi = {10.1109/TVLSI.2018.2864267},
  url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2864267},
  researchr = {https://researchr.org/publication/YabuuchiTFTSN18},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {26},
  number = {11},
  pages = {2335-2344},
}