Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process - researchr publication

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Kodai Yamada, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi. Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. In IEEE International Reliability Physics Symposium, IRPS 2018, Burlingame, CA, USA, March 11-15, 2018. pages 3-1, IEEE, 2018. [doi]

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