An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope - researchr publication authors

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Angxiao Yan, Wei Deng 0001, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi. An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]

This author has not been identified. Look up 'Angxiao Yan' in GoogleThis author has not been identified. Look up 'Wei Deng 0001' in GoogleThis author has not been identified. Look up 'Haikun Jia' in GoogleThis author has not been identified. Look up 'Shiyan Sun' in GoogleThis author has not been identified. It may be one of the following persons:

Chao Tang

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