Angxiao Yan, Wei Deng 0001, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi. An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
@inproceedings{Yan0JSTZFLC23,
title = {An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope},
author = {Angxiao Yan and Wei Deng 0001 and Haikun Jia and Shiyan Sun and Chao Tang and Bufan Zhu and Yu Fu and Hongzhuo Liu and Baoyong Chi},
year = {2023},
doi = {10.23919/VLSITechnologyandCir57934.2023.10185335},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185335},
researchr = {https://researchr.org/publication/Yan0JSTZFLC23},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023},
publisher = {IEEE},
isbn = {978-4-86348-806-9},
}