Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs

Jin-Tai Yan. Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(3):512-525, 2019. [doi]

@article{Yan19-1,
  title = {Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs},
  author = {Jin-Tai Yan},
  year = {2019},
  doi = {10.1109/TCAD.2018.2818728},
  url = {https://doi.org/10.1109/TCAD.2018.2818728},
  researchr = {https://researchr.org/publication/Yan19-1},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {38},
  number = {3},
  pages = {512-525},
}