Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir. Novel memristive logic architectures. In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016. pages 196-199, IEEE, 2016. [doi]
@inproceedings{YangABJ16,
title = {Novel memristive logic architectures},
author = {Xiaohan Yang and Adedotun Adeyemo and Anu Bala and Abusaleh M. Jabir},
year = {2016},
doi = {10.1109/PATMOS.2016.7833687},
url = {http://dx.doi.org/10.1109/PATMOS.2016.7833687},
researchr = {https://researchr.org/publication/YangABJ16},
cites = {0},
citedby = {0},
pages = {196-199},
booktitle = {26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016},
publisher = {IEEE},
isbn = {978-1-5090-0733-2},
}