SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing

Yoon Seok Yang, Hrishikesh Deshpande, Gwan Choi, Paul V. Gratz. SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. IEEE Trans. on CAD of Integrated Circuits and Systems, 37(3):545-558, 2018. [doi]

Authors

Yoon Seok Yang

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Hrishikesh Deshpande

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Gwan Choi

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Paul V. Gratz

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