Yoon Seok Yang, Hrishikesh Deshpande, Gwan Choi, Paul V. Gratz. SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. IEEE Trans. on CAD of Integrated Circuits and Systems, 37(3):545-558, 2018. [doi]
@article{YangDCG18,
title = {SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing},
author = {Yoon Seok Yang and Hrishikesh Deshpande and Gwan Choi and Paul V. Gratz},
year = {2018},
doi = {10.1109/TCAD.2016.2570428},
url = {https://doi.org/10.1109/TCAD.2016.2570428},
researchr = {https://researchr.org/publication/YangDCG18},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {37},
number = {3},
pages = {545-558},
}