Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin. Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014. pages 373-376, IEEE, 2014. [doi]

This author has not been identified. Look up 'Yifan YangGong' in GoogleThis author has not been identified. Look up 'Sebastian Turullols' in GoogleThis author has not been identified. Look up 'Daniel Woo' in GoogleThis author has not been identified. Look up 'Changku Huang' in GoogleThis author has not been identified. Look up 'King C. Yen' in GoogleThis author has not been identified. Look up 'Venkatram Krishnaswamy' in GoogleThis author has not been identified. Look up 'Kalon Holdbrook' in GoogleThis author has not been identified. Look up 'Jinuk Luke Shin' in Google

runs on WebDSL