Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin. Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014. pages 373-376, IEEE, 2014. [doi]
@inproceedings{YangGongTWHYKHS14,
title = {Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor},
author = {Yifan YangGong and Sebastian Turullols and Daniel Woo and Changku Huang and King C. Yen and Venkatram Krishnaswamy and Kalon Holdbrook and Jinuk Luke Shin},
year = {2014},
doi = {10.1109/ASSCC.2014.7008938},
url = {http://dx.doi.org/10.1109/ASSCC.2014.7008938},
researchr = {https://researchr.org/publication/YangGongTWHYKHS14},
cites = {0},
citedby = {0},
pages = {373-376},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014},
publisher = {IEEE},
isbn = {978-1-4799-4090-5},
}