Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion - researchr publication authors

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Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani. Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. In Proceedings of the 1999 Conference on Asia South Pacific Design Automation, January 18-21, 1999, Wanchai, Hong Kong. pages 125, IEEE, 1999. [doi]

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