The following publications are possibly variants of this publication:
- Clock Period Minimization Method of Semi-Synchronous Circuits by Delay InsertionYukihide Kohira, Atsushi Takahashi. ieicet, 88-A(4):892-898, 2005. [doi]
- Minimization of delay insertion in clock period improvement in general-synchronous frameworkYukihide Kohira, Shuhei Tani, Atsushi Takahashi. apccas 2008: 1680-1683 [doi]
- Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous FrameworkYukihide Kohira, Shuhei Tani, Atsushi Takahashi. ieicet, 92-A(4):1106-1114, 2009. [doi]
- Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period MinimizationYukihide Kohira, Atsushi Takahashi. ieicet, 90-A(4):800-807, 2007. [doi]
- Delay variation tolerant clock scheduling for semi-synchronous circuitsH. Matsumura, A. Takahashi. apccas 2002: 165-170 [doi]