Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani. Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. In Proceedings of the 1999 Conference on Asia South Pacific Design Automation, January 18-21, 1999, Wanchai, Hong Kong. pages 125, IEEE, 1999. [doi]
@inproceedings{YodaTK99,
title = {Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion},
author = {Tomoyuki Yoda and Atsushi Takahashi and Yoji Kajitani},
year = {1999},
url = {http://csdl.computer.org/comp/proceedings/asp-dac/1999/2329/00/23290125abs.htm},
researchr = {https://researchr.org/publication/YodaTK99},
cites = {0},
citedby = {0},
pages = {125},
booktitle = {Proceedings of the 1999 Conference on Asia South Pacific Design Automation, January 18-21, 1999, Wanchai, Hong Kong},
publisher = {IEEE},
}