A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33% - researchr publication authors

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Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba. A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. J. Solid-State Circuits, 36(3):503-509, 2001. [doi]

This author has not been identified. Look up 'Yuji Yokoyama' in GoogleThis author has not been identified. Look up 'Nobutaka Itoh' in GoogleThis author has not been identified. Look up 'Masatoshi Hasegawa' in GoogleThis author has not been identified. Look up 'Masahiro Katayama' in GoogleThis author has not been identified. Look up 'Hiroshi Akasaki' in GoogleThis author has not been identified. Look up 'Masayuki Kaneda' in GoogleThis author has not been identified. Look up 'Toshitsugu Ueda' in GoogleThis author has not been identified. Look up 'Yousuke Tanaka' in GoogleThis author has not been identified. Look up 'Eiji Yamasaki' in GoogleThis author has not been identified. Look up 'Masaya Todokoro' in GoogleThis author has not been identified. Look up 'Keinosuke Toriyama' in GoogleThis author has not been identified. Look up 'Hiroshi Miki' in GoogleThis author has not been identified. Look up 'Masayoshi Yagyu' in GoogleThis author has not been identified. Look up 'Kazumasa Takashima' in GoogleThis author has not been identified. Look up 'Toru Kobayashi' in GoogleThis author has not been identified. Look up 'Syuichi Miyaoka' in GoogleThis author has not been identified. Look up 'Nobuo Tamba' in Google

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