Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba. A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%. J. Solid-State Circuits, 36(3):503-509, 2001. [doi]
@article{YokoyamaIHKAKUT01,
title = {A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%},
author = {Yuji Yokoyama and Nobutaka Itoh and Masatoshi Hasegawa and Masahiro Katayama and Hiroshi Akasaki and Masayuki Kaneda and Toshitsugu Ueda and Yousuke Tanaka and Eiji Yamasaki and Masaya Todokoro and Keinosuke Toriyama and Hiroshi Miki and Masayoshi Yagyu and Kazumasa Takashima and Toru Kobayashi and Syuichi Miyaoka and Nobuo Tamba},
year = {2001},
doi = {10.1109/4.910489},
url = {https://doi.org/10.1109/4.910489},
researchr = {https://researchr.org/publication/YokoyamaIHKAKUT01},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {36},
number = {3},
pages = {503-509},
}