A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

Changsik Yoo, Kye-Hyun Kyung, Kyunam Lim, Hi-Choon Lee, Joon-Wan Chai, Nak-Won Heo, Dong-jin Lee, Chang-Hyun Kim. A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. J. Solid-State Circuits, 39(6):941-951, 2004. [doi]

Authors

Changsik Yoo

This author has not been identified. Look up 'Changsik Yoo' in Google

Kye-Hyun Kyung

This author has not been identified. Look up 'Kye-Hyun Kyung' in Google

Kyunam Lim

This author has not been identified. Look up 'Kyunam Lim' in Google

Hi-Choon Lee

This author has not been identified. Look up 'Hi-Choon Lee' in Google

Joon-Wan Chai

This author has not been identified. Look up 'Joon-Wan Chai' in Google

Nak-Won Heo

This author has not been identified. Look up 'Nak-Won Heo' in Google

Dong-jin Lee

This author has not been identified. Look up 'Dong-jin Lee' in Google

Chang-Hyun Kim

This author has not been identified. Look up 'Chang-Hyun Kim' in Google