A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara. A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 100-590, IEEE, 2007. [doi]

This author has not been identified. Look up 'Yutaka Yoshida' in GoogleThis author has not been identified. Look up 'Tatsuya Kamei' in GoogleThis author has not been identified. Look up 'Kiyoshi Hayase' in GoogleThis author has not been identified. Look up 'Shinichi Shibahara' in GoogleThis author has not been identified. Look up 'Osamu Nishii' in GoogleThis author has not been identified. Look up 'Toshihiro Hattori' in GoogleThis author has not been identified. Look up 'Atsushi Hasegawa' in GoogleThis author has not been identified. Look up 'Masashi Takada' in GoogleThis author has not been identified. Look up 'Naohiko Irie' in GoogleThis author has not been identified. Look up 'Kunio Uchiyama' in GoogleThis author has not been identified. Look up 'Toshihiko Odaka' in GoogleThis author has not been identified. Look up 'Kiwamu Takada' in GoogleThis author has not been identified. Look up 'Keiji Kimura' in GoogleThis author has not been identified. Look up 'Hironori Kasahara' in Google

runs on WebDSL