Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara. A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 100-590, IEEE, 2007. [doi]
@inproceedings{YoshidaKHSNHHTIUOTKK07,
title = {A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption},
author = {Yutaka Yoshida and Tatsuya Kamei and Kiyoshi Hayase and Shinichi Shibahara and Osamu Nishii and Toshihiro Hattori and Atsushi Hasegawa and Masashi Takada and Naohiko Irie and Kunio Uchiyama and Toshihiko Odaka and Kiwamu Takada and Keiji Kimura and Hironori Kasahara},
year = {2007},
doi = {10.1109/ISSCC.2007.373607},
url = {http://dx.doi.org/10.1109/ISSCC.2007.373607},
researchr = {https://researchr.org/publication/YoshidaKHSNHHTIUOTKK07},
cites = {0},
citedby = {0},
pages = {100-590},
booktitle = {2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007},
publisher = {IEEE},
isbn = {1-4244-0853-9},
}