Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro. An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. In Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012. pages 381-384, IEEE, 2012. [doi]
@inproceedings{YoshiokaSSKI12, title = {An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator}, author = {Kentaro Yoshioka and Akira Shikata and Ryota Sekimoto and Tadahiro Kuroda and Hiroki Ishikuro}, year = {2012}, doi = {10.1109/ESSCIRC.2012.6341365}, url = {http://dx.doi.org/10.1109/ESSCIRC.2012.6341365}, researchr = {https://researchr.org/publication/YoshiokaSSKI12}, cites = {0}, citedby = {0}, pages = {381-384}, booktitle = {Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012}, publisher = {IEEE}, isbn = {978-1-4673-2212-6}, }