An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator - researchr publication related

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Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro. An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. In Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012. pages 381-384, IEEE, 2012. [doi]

The following publications are possibly variants of this publication:

A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADCKentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro. aspdac 2013: 111-112 [doi]

An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOSKentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro. tvlsi, 23(2):356-368, 2015. [doi]

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