The design and transport latency analysis of a locality-aware network on chip architecture

Chung-Ping Young, Chung-Chu Chia, Yen-Bor Lin. The design and transport latency analysis of a locality-aware network on chip architecture. In IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2008, Macao, China, November 30 2008 - December 3, 2008. pages 1272-1275, IEEE, 2008. [doi]

Abstract

Abstract is missing.