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A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency

K. Zaitsu, A. Matsumoto, M. Nishida, Y. Tanaka, H. Yamashita, Y. Satake, T. Watanabe, K. Araki, N. Nei, K. Nakazawa, J. Yamamoto, M. Uehara, H. Kawashima, Y. Kobayashi, T. Hirano, K. Tatani. A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 286-287, IEEE, 2022. [doi]

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K. Zaitsu

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A. Matsumoto

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M. Nishida

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Y. Tanaka

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H. Yamashita

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Y. Satake

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T. Watanabe

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K. Araki

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N. Nei

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K. Nakazawa

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J. Yamamoto

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M. Uehara

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H. Kawashima

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Y. Kobayashi

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T. Hirano

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K. Tatani

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