K. Zaitsu, A. Matsumoto, M. Nishida, Y. Tanaka, H. Yamashita, Y. Satake, T. Watanabe, K. Araki, N. Nei, K. Nakazawa, J. Yamamoto, M. Uehara, H. Kawashima, Y. Kobayashi, T. Hirano, K. Tatani. A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency. In IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022. pages 286-287, IEEE, 2022. [doi]
@inproceedings{ZaitsuMNTYSWANN22,
title = {A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide-Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency},
author = {K. Zaitsu and A. Matsumoto and M. Nishida and Y. Tanaka and H. Yamashita and Y. Satake and T. Watanabe and K. Araki and N. Nei and K. Nakazawa and J. Yamamoto and M. Uehara and H. Kawashima and Y. Kobayashi and T. Hirano and K. Tatani},
year = {2022},
doi = {10.1109/VLSITechnologyandCir46769.2022.9830372},
url = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830372},
researchr = {https://researchr.org/publication/ZaitsuMNTYSWANN22},
cites = {0},
citedby = {0},
pages = {286-287},
booktitle = {IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022},
publisher = {IEEE},
isbn = {978-1-6654-9772-5},
}