A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr. A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. J. Solid-State Circuits, 41(1):146-151, 2006. [doi]

Authors

Kevin Zhang

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Uddalak Bhattacharya

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Zhanping Chen

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Fatih Hamzaoglu

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Daniel Murray

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Narendra Vallepalli

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Yih Wang

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Bo Zheng

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Mark Bohr

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