An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process - researchr publication authors

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Yuejun Zhang, Ding Dailu, Pan Zhao, Pengjun Wang, Qiaoyan Yu. An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics Journal, 78:26-34, 2018. [doi]

This author has not been identified. Look up 'Yuejun Zhang' in GoogleThis author has not been identified. Look up 'Ding Dailu' in GoogleThis author has not been identified. Look up 'Pan Zhao' in GoogleThis author has not been identified. Look up 'Pengjun Wang' in GoogleThis author has not been identified. Look up 'Qiaoyan Yu' in Google

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