An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process

Yuejun Zhang, Ding Dailu, Pan Zhao, Pengjun Wang, Qiaoyan Yu. An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics Journal, 78:26-34, 2018. [doi]

@article{ZhangDZWY18,
  title = {An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process},
  author = {Yuejun Zhang and Ding Dailu and Pan Zhao and Pengjun Wang and Qiaoyan Yu},
  year = {2018},
  doi = {10.1016/j.mejo.2018.05.016},
  url = {https://doi.org/10.1016/j.mejo.2018.05.016},
  researchr = {https://researchr.org/publication/ZhangDZWY18},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Journal},
  volume = {78},
  pages = {26-34},
}