An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process

Yuejun Zhang, Ding Dailu, Pan Zhao, Pengjun Wang, Qiaoyan Yu. An ultra-low power multiplier using multi-valued adiabatic logic in 65 nm CMOS process. Microelectronics Journal, 78:26-34, 2018. [doi]

Abstract

Abstract is missing.