The following publications are possibly variants of this publication:
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- A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC CodesZhongfeng Wang, Zhiqiang Cui. tvlsi, 15(4):483-488, 2007. [doi]
- Efficient column-layered decoders for single block-row quasi-cyclic LDPC codesChuan Zhang, Xiaohu You, Zhongfeng Wang. iscas 2014: 413-416 [doi]
- Low complexity, high speed decoder architecture for quasi-cyclic LDPC codesZhongfeng Wang, Qing-Wei Jia. iscas 2005: 5786-5789 [doi]
- Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codesXinmiao Zhang, Fang Cai. icassp 2010: 1506-1509 [doi]
- Nonbinary LDPC Code Decoder Architecture With Efficient Check Node ProcessingKai He, Jin Sha, Zhongfeng Wang. tcas, 59-II(6):381-385, 2012. [doi]