Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA - researchr publication authors

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Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura. Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. In 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018. pages 184-189, IEEE, 2018. [doi]

This author has not been identified. Look up 'Zhifeng Zhang' in GoogleThis author has not been identified. Look up 'Dajiang Zhou' in GoogleThis author has not been identified. Look up 'Shihao Wang' in GoogleThis author has not been identified. Look up 'Shinji Kimura' in Google

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