Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura. Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA. In 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018. pages 184-189, IEEE, 2018. [doi]
@inproceedings{ZhangZWK18,
title = {Quad-multiplier packing based on customized floating point for convolutional neural networks on FPGA},
author = {Zhifeng Zhang and Dajiang Zhou and Shihao Wang and Shinji Kimura},
year = {2018},
doi = {10.1109/ASPDAC.2018.8297303},
url = {https://doi.org/10.1109/ASPDAC.2018.8297303},
researchr = {https://researchr.org/publication/ZhangZWK18},
cites = {0},
citedby = {0},
pages = {184-189},
booktitle = {23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018},
publisher = {IEEE},
isbn = {978-1-5090-0602-1},
}