A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS

Xiaoteng Zhao, Yong Chen 0005, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins. A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. J. Solid-State Circuits, 57(5):1358-1371, 2022. [doi]

Abstract

Abstract is missing.