Verification of timed circuits with failure-directed abstractions

Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda. Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems, 25(3):403-412, 2006. [doi]

@article{ZhengMWLY06,
  title = {Verification of timed circuits with failure-directed abstractions},
  author = {Hao Zheng and Chris J. Myers and David Walter and Scott Little and Tomohiro Yoneda},
  year = {2006},
  doi = {10.1109/TCAD.2005.854638},
  url = {http://dx.doi.org/10.1109/TCAD.2005.854638},
  tags = {abstraction},
  researchr = {https://researchr.org/publication/ZhengMWLY06},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {25},
  number = {3},
  pages = {403-412},
}