A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis

Riyong Zheng, Chenghao Wang 0006, Jun Han 0003, Xiaoyang Zeng. A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis. In 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. pages 1-3, IEEE, 2019. [doi]

@inproceedings{ZhengWHZ19,
  title = {A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis},
  author = {Riyong Zheng and Chenghao Wang 0006 and Jun Han 0003 and Xiaoyang Zeng},
  year = {2019},
  doi = {10.1109/ASICON47005.2019.8983681},
  url = {https://doi.org/10.1109/ASICON47005.2019.8983681},
  researchr = {https://researchr.org/publication/ZhengWHZ19},
  cites = {0},
  citedby = {0},
  pages = {1-3},
  booktitle = {13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-0735-6},
}