A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme

Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda. A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. In FPGA. pages 248, 2003. [doi]

@inproceedings{ZhouCYGCMMKG03,
  title = {A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme},
  author = {Kuan Zhou and Michael Chu and Chao You and Jong-Ru Guo and Channakeshav and John Mayega and John F. McDonald and Russell P. Kraft and Bryan S. Goda},
  year = {2003},
  doi = {10.1145/611817.611883},
  url = {http://doi.acm.org/10.1145/611817.611883},
  researchr = {https://researchr.org/publication/ZhouCYGCMMKG03},
  cites = {0},
  citedby = {0},
  pages = {248},
  booktitle = {FPGA},
}