D. Zhou, Wei Li, W. Cai, N. Guo. An efficient balanced truncation realization algorithm for interconnect model order reduction. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 383-386, IEEE, 2001. [doi]
@inproceedings{ZhouLCG01,
title = {An efficient balanced truncation realization algorithm for interconnect model order reduction},
author = {D. Zhou and Wei Li and W. Cai and N. Guo},
year = {2001},
doi = {10.1109/ISCAS.2001.922065},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2001.922065},
researchr = {https://researchr.org/publication/ZhouLCG01},
cites = {0},
citedby = {0},
pages = {383-386},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia},
publisher = {IEEE},
isbn = {0-7803-6685-9},
}