An efficient balanced truncation realization algorithm for interconnect model order reduction

D. Zhou, Wei Li, W. Cai, N. Guo. An efficient balanced truncation realization algorithm for interconnect model order reduction. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 383-386, IEEE, 2001. [doi]

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