Junheng Zhu, Woo-seok Choi, Pavan Kumar Hanumolu. 2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS. J. Solid-State Circuits, 54(8):2186-2194, 2019. [doi]
@article{ZhuCH19-0,
title = {2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS},
author = {Junheng Zhu and Woo-seok Choi and Pavan Kumar Hanumolu},
year = {2019},
doi = {10.1109/JSSC.2019.2915021},
url = {https://doi.org/10.1109/JSSC.2019.2915021},
researchr = {https://researchr.org/publication/ZhuCH19-0},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {54},
number = {8},
pages = {2186-2194},
}