Zeljko Zilic, Katarzyna Radecka. : Identifying redundant gate replacements in verification by error modeling. In Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001. pages 803-812, IEEE Computer Society, 2001.
@inproceedings{ZilicR01, title = {: Identifying redundant gate replacements in verification by error modeling}, author = {Zeljko Zilic and Katarzyna Radecka}, year = {2001}, tags = {modeling}, researchr = {https://researchr.org/publication/ZilicR01}, cites = {0}, citedby = {0}, pages = {803-812}, booktitle = {Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001}, publisher = {IEEE Computer Society}, isbn = {0-7803-7169-0}, }