Abstract is missing.
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- Area - Time - Power and Design effort: the basic tradeoffs in Application Specific SystemsMichael J. Flynn. 3 [doi]
- Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor SystemsThomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich. 9-14 [doi]
- Expression Synthesis in Process Networks generated by LAURAClaudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere. 15-21 [doi]
- Artificial Deadlock Detection in Process Networks for ECLIPSEBharath N, Nagaraju Bussa. 22-27 [doi]
- Hardware/Software Interface for Multi-Dimensional Processor ArraysAlain Darte, Steven Derrien, Tanguy Risset. 28-35 [doi]
- Casablanca II: Implementation of a Real-Time RISCKiyofumi Tanaka. 36-42 [doi]
- Behavioral specification of control interface for signal processing applicationsJérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere. 43-49 [doi]
- Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable HardwareMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. 50-59 [doi]
- A SW/Configware Codesign Methodology for Control Dominated ApplicationsKarim Ben Chehida, Michel Auguin. 56-64 [doi]
- Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media ProcessingSamarjit Chakraborty. 65-72 [doi]
- Communication-Centric SoC Design for Nanoscale DomainÜmit Y. Ogras, Jingcao Hu, Radu Marculescu. 73-78 [doi]
- Using TLM for Exploring Bus-based SoC Communication ArchitecturesSudeep Pasricha, Mohamed Ben-Romdhane. 79-85 [doi]
- Exploring Design Space of VLIW ArchitecturesGiuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti. 86-91 [doi]
- The Midlifekicker Microarchitecture Evaluation MetricStamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev. 92-100 [doi]
- Design of a Hardware Accelerator for Density Based Clustering ApplicationsJayaprakash Pisharath, Alok N. Choudhary. 101-106 [doi]
- Complex Fixed-Point Matrix Inversion Using Transport Triggered ArchitectureAdrian Burian, Perttu Salmela, Jarmo Takala. 107-112 [doi]
- A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering CoprocessorKuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai. 113-118 [doi]
- Eliminating Sorting in IP Lookup Devices using Partitioned TableEnrico Ng, Gyungho Lee. 119-126 [doi]
- Generating Efficient Custom FPGA Soft-Cores for Control-Dominated ApplicationsLudovic L Hours. 127-133 [doi]
- Multiply-Accumulate Architecture for a Special Class of Optimal Extension FieldsMoboluwaji O. Sanu, Earl E. Swartzlander Jr.. 134-139 [doi]
- Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video EncodingNikolaos Kavvadias, Spiridon Nikolaidis. 140-145 [doi]
- Instruction Set Architecture Enhancements for Video ProcessingJan-Willem van de Waerdt, Stamatis Vassiliadis. 146-153 [doi]
- Instruction Set Customization of Application Specific Processors for Network Processing: A Case StudyMohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers. 154-160 [doi]
- Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable ArraysGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis. 161-168 [doi]
- Architectural Support for Accelerating Congestion Control Applications in Network ProcessorsByeong Kil Lee, Lizy Kurian John, Eugene John. 169-178 [doi]
- Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video ApplicationAndy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina. 179-184 [doi]
- A Low-Power Processor Architecture Optimized forWireless DevicesAristides Efthymiou, Jim D. Garside, Ioannis Papaefstathiou. 185-190 [doi]
- CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded SystemsVida Kianzad, Shuvra S. Bhattacharyya, Gang Qu. 191-197 [doi]
- Via-Aware Global Routing for Good VLSI Manufacturability and High YieldYang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan. 198-203 [doi]
- Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate DesignsThi Nguyen, Kaijian Shi. 204-212 [doi]
- Zippy - A coarse-grained reconfigurable array with support for hardware virtualizationChristian Plessl, Marco Platzner. 213-218 [doi]
- An Image Processor for Digital FilmAmilcar do Carmo Lucas, Rolf Ernst. 219-224 [doi]
- On Estimations for Compiling Software to FPGA-based SystemsJoão M. P. Cardoso. 225-230 [doi]
- A Programmable DSP Architecture for Wireless Communication SystemsAmir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka. 231-238 [doi]
- Customising Application-Speci.c Multiprocessor Systems: a Case StudyAndreas Fidjeland, Wayne Luk. 239-246 [doi]
- Faults, Error Bounds and Reliability of Nanoelectronic CircuitsJie Han, Erin Taylor, Jianbo Gao, José A. B. Fortes. 247-253 [doi]
- Logic Models Supporting the Design of MOBILE-based RTD CircuitsMaria J. Avedillo, José M. Quintana, Héctor Pettenghi. 254-259 [doi]
- CONAN - A Design Exploration Framework for Reliable Nano-ElectronicsSorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf, Manfred Glesner, A. Rubio. 260-267 [doi]
- Analytical approach to massively parallel architectures for nanotechnologiesBjørn Jager, Jörg-Christian Niemann, Ulrich Rückert. 268-275 [doi]
- On the Advantages of Serial Architectures for Low-Power Reliable ComputationsValeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal. 276-281 [doi]
- Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal SystemsP. M. Kelly, T. Martin McGinnity, Liam P. Maguire. 282-287 [doi]
- Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA)Konrad Walus, Mike Mazur, Gabriel Schulhof, Graham A. Jullien. 288-293 [doi]
- High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling TechnologyCor Meenderinck, Sorin Cotofana, Casper Lageweg. 294-302 [doi]
- Multiplication Algorithms for Radix-2 RN-Codings and Two s Complement Multiplication Algorithms for Radix-2 RN-Codings and Two s ComplementJean-Luc Beuchat, Jean-Michel Muller. 303-308 [doi]
- Decimal Floating-Point Square Root Using Newton-Raphson IterationLiang-Kai Wang, Michael J. Schulte. 309-315 [doi]
- Variable Radix Real and Complex Digit-Recurrence DivisionMilos D. Ercegovac, Jean-Michel Muller. 316-321 [doi]
- On-line Multioperand Addition Based on On-line Full AddersJulio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata. 322-327 [doi]
- Table-based polynomials for fast hardware function evaluationJérémie Detrey, Florent de Dinechin. 328-333 [doi]
- Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of xRomain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon. 334-342 [doi]
- Architectural Extensions for Elliptic Curve Cryptography over GF(2:::m:::) on 8-bit MicroprocessorsHans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang Shantz, Vipul Gupta. 343-349 [doi]
- Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2:::n:::)Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede. 350-355 [doi]
- On-Chip Lookup Tables for Fast Symmetric-Key EncryptionA. Murat Fiskiran, Ruby B. Lee. 356-363 [doi]
- Instruction Set Extensions for Reed-Solomon Encoding and DecodingSuman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner. 364-369 [doi]
- 256-State Rate 1/2 Viterbi Decoder on TTA ProcessorPerttu Salmela, Tuomas Järvinen, Teemu Sipilä, Jarmo Takala. 370-378 [doi]
- Recursive Filtering on a Vector DSP with Linear SpeedupM. Van Der Horst, Kees van Berkel, Johan Lukkien, Rudolf H. Mak. 379-386 [doi]
- A Fault-Tolerant Modulus Replication Complex FIR FilterIan Steiner, P. Chan, Laurent Imbert, Graham A. Jullien, Vassil S. Dimitrov, G. H. McGibney. 387-392 [doi]
- Performance Comparison of SIMD Implementations of the Discrete Wavelet TransformAsadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis. 393-398 [doi]
- Real-time H/W Implementation of the Approximate Discrete Radon TransformMichael T. Frederick, Nathan A. VanderHorn, Arun K. Somani. 399-404 [doi]
- A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip MultiprocessorTom R. Jacobs, José L. Núñez-Yáñez. 405-410 [doi]
- Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video CodecJosé L. Núñez-Yáñez, Vassilios A. Chouliaras. 411-416 [doi]