Abstract is missing.
- The case for application specific computingEarl Swartzlander. 2-9 [doi]
- Implementation of a VLSI polynomial evaluator for real-time applicationsGuy Corbaz, Jean Duprat, Bertrand Hochet, Jean-Michel Muller. 13-24 [doi]
- A defect tolerant systolic array implementation for real time image processingV. Hecht, Karsten Rönner, Peter Pirsch. 25-39 [doi]
- The systematic design of a motion estimation array architectureJan Rosseel, Francky Catthoor, Hugo De Man. 40-54 [doi]
- Transformation of systolic algorithms for interleaving partitionsAgustín Fernández, José M. Llabería, Juan J. Navarro, Miguel Valero-García. 56-71 [doi]
- Mapping different node types of dependence graphs into the same processing elementUwe Vehlies. 72-86 [doi]
- Mapping FIR filtering on systolic ringsAngelos P. Varvitsiotis, Sergios Theodoridis, Rami G. Melhem. 87-101 [doi]
- The missing dimension in real-time signal processing architecturesJeff Robinson, Keith Rouse, Paul Jordan, Terry Montlick. 104-115 [doi]
- A wave digital filter three-port adaptor with fine grained pipeliningRajinder Jit Singh, John V. McCanny. 116-128 [doi]
- The Arithmetic Cube: error analysis and simulationMohan Vishwanath, Robert Michael Owens, Mary Jane Irwin. 129-143 [doi]
- Biological information signal processorE. T. Chow, Tim Hunkapiller, J. Peterson, Michael S. Waterman. 144-160 [doi]
- Parallel digital implementations of neural networksK. Wojtek Przytula. 162-176 [doi]
- Partitioning schemes for circuit simulation on a multiprocessor arrayRicardo Telichevesky, Prathima Agrawal, John A. Trotter. 177-183 [doi]
- Parallel implementations of discrete relaxation technique on fixed size processor arraysWei-Ming Lin, Viktor K. Prasanna. 184-198 [doi]
- Parallel strong orientation on a mesh connected computerManfred Schimmler. 199-211 [doi]
- Parallel array architectures for motion estimationTeresa H. Y. Meng, Andy C. Hung. 214-235 [doi]
- CAPMA: a content-addressable pattern match architecture for production systemsChie Dou, Shao-Ming Wu. 236-248 [doi]
- High speed implementation of 1-D and 2-D morphological operationsJohn A. Vlontzos. 249-262 [doi]
- Pipelining and transposing heterogeneous array circuitsWayne W. C. Luk. 263-277 [doi]
- A decoupled access/execute processor for matrix algorithms: architecture and programmingJaime H. Moreno, Miguel E. Figueroa. 281-295 [doi]
- Uniform but non-local DAGS: a trade-off between pure systolic and SIMD solutionsTanguy Risset, Yves Robert. 296-308 [doi]
- A TSP engine for performing tabu searchVijay Karamcheti, Miroslaw Malek. 309-321 [doi]
- Synthesis of systolic arrays by equation transformationsCatherine Dezan, Eric Gautrin, Hervé Le Verge, Patrice Quinton, Yannick Saouter. 324-337 [doi]
- Automatic formal verification of systolic array designsNam Ling, Fuyau Lin, Timothy K. Shih, Ruth E. Davis. 338-354 [doi]
- Consistency in dataflow graphsEdward A. Lee. 355-369 [doi]
- Synthesizing systolic arrays: some recent developmentsAlain Darte, Tanguy Risset, Yves Robert. 372-386 [doi]
- A design method for on-line reconfigurable array processorsJens Franzen. 387-401 [doi]
- Processor clustering for the design of optimal fixed-size systolic arraysJichun Bu, Ed F. Deprettere. 402-413 [doi]
- A 40 megasample IIR filter chipO. C. McNally, John V. McCanny, Roger F. Woods. 416-430 [doi]
- GFLOPS: a general flexible linearly organized parallel structure for imagesDominique Houzet, Jean-Luc Basille, Jean-Yves Latil. 431-444 [doi]
- Fast generation of long sorted runs for sorting a large fileYen-Chun Lin, Yu-Ho Cheng. 445-456 [doi]
- A modular systolic 2-D torus for the general knapsack problemRumen Andonov, Frédéric Gruau. 458-472 [doi]
- A systolic algorithm for the triangular Stein equationJosé L. Hueso, Gloria Martínez, Vicente Hernández. 473-484 [doi]
- Systolic architecture for adaptive eigenstructure decomposition based on simultaneous iteration methodS. Erlich, K. Yao. 485-495 [doi]